Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/5qhpfc56jxx2hqlwq2qvhnsy82zxvnwd-verilator-4.204.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/f0hg2i41k67lmhjjqyzmdilnchv49c59-verilator-4.204.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/kqk0r8shncw495dw615p609ja4gf6kpn-verilator-4.204.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/lqq3gp7dabyb35mdchh46khs1v125nhq-verilator-4.204.drv | |
powerpc64le-linux | /gnu/store/z6s3j7wr79bihi85ra1qy3p57g8499z1-verilator-4.204.drv | ||
mips64el-linux | /gnu/store/4cmbpjx1gjf6mz32sfh4ah5fklhckzvv-verilator-4.204.drv | ||
i686-linux | /gnu/store/f0w74shz4rm62j2hvqy1s1lhj1sz5dxs-verilator-4.204.drv | ||
i586-gnu | /gnu/store/9nqi4s5svwpaz17brrwf3grc1p91h2aw-verilator-4.204.drv | ||
armhf-linux | /gnu/store/ks6zjhrbg3l3v7axfk2id0d80405dfks-verilator-4.204.drv | ||
aarch64-linux | /gnu/store/m9y97vlaldj3l1m1qzkam0c1d4cslvp4-verilator-4.204.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes | |
description Validate package descriptions | use @code or similar ornament instead of quotes |