Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/w412fh90p4hm9b1jv1398i3rvaki68xv-verilator-4.110.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/891l7lqdhpph48wws8a2k3ndy7zw6s9i-verilator-4.110.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/gkhh7j5jc4m6mx4yn6rf80aqvjjyb0c2-verilator-4.110.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/wwl0y9kvbl0lbb1wn7mwh1lvmng46kb4-verilator-4.110.drv | |
powerpc64le-linux | /gnu/store/z48zf7pp8vhhckrqnc900y6i5jzhy9y3-verilator-4.110.drv | ||
mips64el-linux | /gnu/store/6z87hfsgnf3g4x4g2y2gqy4vpd5699r5-verilator-4.110.drv | ||
i686-linux | /gnu/store/759zhw54vsy0ckny6x196nz6mb3a2c3i-verilator-4.110.drv | ||
i586-gnu | /gnu/store/prrmlx247v227j5rji7yi4lsjc16d0gb-verilator-4.110.drv | ||
armhf-linux | /gnu/store/6glycnhj747af6x7gk4j1y9j6775d2mg-verilator-4.110.drv | ||
aarch64-linux | /gnu/store/1hjnxvw9s2mx79ffqf7vjnh3wcm251w4-verilator-4.110.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes | |
description Validate package descriptions | use @code or similar ornament instead of quotes |