Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/h3g1b0xqbpdsgj609g6zj276lwcii8zk-verilator-4.110.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/vk9ayqnxid6pgil7qk3p88ga8dqpcm51-verilator-4.110.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/s55rmzv8fd6vdakrn6wyjffcqsigxcrx-verilator-4.110.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/hjdg7x1dmy4faph76lhx6hiwg78ra49x-verilator-4.110.drv | |
powerpc64le-linux | /gnu/store/fzxw7022gx4f192azl72kkpwbjq84yvr-verilator-4.110.drv | ||
mips64el-linux | /gnu/store/ip1nxqq1xvhdyygx96qcp4160rvyai0x-verilator-4.110.drv | ||
i686-linux | /gnu/store/np4j260r323pg14jadrv88y055r41f0f-verilator-4.110.drv | ||
i586-gnu | /gnu/store/ird39ifn5amlfzffgfnz5nglgdwn85sq-verilator-4.110.drv | ||
armhf-linux | /gnu/store/lj071m507582yygy31dpc4irbr3svglz-verilator-4.110.drv | ||
aarch64-linux | /gnu/store/x1ybnrvhyg19qx8xcsfpss9f1p9xy921-verilator-4.110.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes | |
description Validate package descriptions | use @code or similar ornament instead of quotes |