Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/zm3q10rnb92ghljvcna8jsis4b9cf0i0-verilator-4.108.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/r3xikbigs4rfpm9w6hzjsylz5i4px1n4-verilator-4.108.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/67azzmi1k0bkigcq1w7i13gyqz6nx5iv-verilator-4.108.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/l6bp0pn1gvwnbxy3j7x90fq5knw5gayn-verilator-4.108.drv | |
mips64el-linux | /gnu/store/dxdhqmn33jhd0brxvxx17ciw7k1s008y-verilator-4.108.drv | ||
i686-linux | /gnu/store/h5b9bg43pzpgkrh820gaihjpr0p067x6-verilator-4.108.drv | ||
i586-gnu | /gnu/store/v834546jzng019payixhf5h5rra7y35b-verilator-4.108.drv | ||
armhf-linux | /gnu/store/0hdvnzl3z2nclwwp49sifrvzksbhx99h-verilator-4.108.drv | ||
aarch64-linux | /gnu/store/c3y5n5jcidmgkajsh3q3k1gjd1i1h14z-verilator-4.108.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes |