Language

Package: verilator @ 4.108

Synopsis

Fast Verilog/SystemVerilog simulator

Description

Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp and .h files, the ``Verilated'' code.

The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.

Home page
https://www.veripool.org/projects/verilator/
Location
gnu/packages/fpga.scm (line: 503, column: 2)
License

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