Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/cn3km80fszwjz4gw66yiqha6wd68bcl8-verilator-4.204.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/z1wsisjwzn3rr3z9p1g24qv2fvpbfdvy-verilator-4.204.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/wgw6x87gwi06ihdwqnz2dia1jd02yzbf-verilator-4.204.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/l5mcib87yxbp9pwaad4r7p12bhdif23m-verilator-4.204.drv | |
powerpc-linux | /gnu/store/n7vx356vf1p0yz2fwsf23q9q2qp3cckn-verilator-4.204.drv | ||
powerpc64le-linux | /gnu/store/djb7nc0lyrlpwnpmckqcfc7kakfbbv8s-verilator-4.204.drv | ||
mips64el-linux | /gnu/store/qqdhd5gz7rd804v2vw0pv5i07yhayry8-verilator-4.204.drv | ||
i686-linux | /gnu/store/75j2yyz5fcd336jbs093bk55azcwwbmn-verilator-4.204.drv | ||
i586-gnu | /gnu/store/ppjzq11c91zslkcyh02g8chczyblc707-verilator-4.204.drv | ||
armhf-linux | /gnu/store/7zgy47j4av3r40i49m12s9y9nd37v6zz-verilator-4.204.drv | ||
aarch64-linux | /gnu/store/77jdpps9d9n3vjzkjavssmxhx4dvcyj4-verilator-4.204.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes | |
input-labels Identify input labels that do not match package names | label 'gettext' does not match package name 'gettext-minimal' |