Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/rffpi6l1kpjj6wvmjzkiqn84y84z5380-verilator-4.204.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/8jf5xp2sicgb40p32z5wrxfsnskrcnav-verilator-4.204.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/llx999cmm9g7z6kfsm79x5173j3h0l02-verilator-4.204.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/gyl4zd1ggnb7bl42w7vj8c7xk3jrk2z1-verilator-4.204.drv | |
powerpc64le-linux | /gnu/store/aav531fj7pmyikdb4n2i5phdc7sq7rc7-verilator-4.204.drv | ||
mips64el-linux | /gnu/store/9wp6kxzbd7qqzxssqwnd77b8dn4p0im4-verilator-4.204.drv | ||
i686-linux | /gnu/store/psilz78ksjyq6fvm0gbqrf7kl7i0bn6g-verilator-4.204.drv | ||
i586-gnu | /gnu/store/cbcz172g6dd1dgsk6v2yfqws6rwkfpa6-verilator-4.204.drv | ||
armhf-linux | /gnu/store/k8spkk9s690r3k5g22afdjikiakyg8ii-verilator-4.204.drv | ||
aarch64-linux | /gnu/store/z537mzf8qjhrm6j51i7g0xnb5z325wk0-verilator-4.204.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes |