Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/a333fgpsd79p4pf4i1y51zrh7gkjf58v-verilator-4.204.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/a4xw53g59s72v1nphj9vaz27d773dx4y-verilator-4.204.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/n7c12cfakqhnrs0rfylwas9ymmwdhr7x-verilator-4.204.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/cnrsqms09jinsyy5yilyfhhhy3mqhvp0-verilator-4.204.drv | |
powerpc64le-linux | /gnu/store/6hknpz4dzkxakj5v8jrc909s5ph0n681-verilator-4.204.drv | ||
mips64el-linux | /gnu/store/n2fn170sfmlb39fjl7yhygf92q77rwwa-verilator-4.204.drv | ||
i686-linux | /gnu/store/8azwrhi6a5x9606zvgjsz30599rjzllr-verilator-4.204.drv | ||
i586-gnu | /gnu/store/cfqfa9x2m30fw6fic7bk9k34q9jhfcs0-verilator-4.204.drv | ||
armhf-linux | /gnu/store/d8diilh6hdw64rzg9jkrb5z4hmi7wawa-verilator-4.204.drv | ||
aarch64-linux | /gnu/store/syhzgxkmxq08hv0w42xmrw9fi02xqhrg-verilator-4.204.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes | |
description Validate package descriptions | use @code or similar ornament instead of quotes |