Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/824kj7nrf9hkbkr5bbipsn44yk2zdnaf-verilator-4.108.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/swfxx1g6fznybq0r524sp7dvydixyp6p-verilator-4.108.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/gqbyklphgskyd6ibm5w6khqw333vsc89-verilator-4.108.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/99m1lpxjj8smnajyamv2hpnsgvprfc3g-verilator-4.108.drv | |
mips64el-linux | /gnu/store/jam420f8qbbhyy6937xqbb7wz3zf8ifd-verilator-4.108.drv | ||
i686-linux | /gnu/store/rgs4py3nnbqzqy5hv415a39qi8c4lgxd-verilator-4.108.drv | ||
i586-gnu | /gnu/store/d4g73ij7b1y944a8imwxxwrsvasr7qbl-verilator-4.108.drv | ||
armhf-linux | /gnu/store/d23x8sh8bfmsh70b2c47biwwf7r8gx19-verilator-4.108.drv | ||
aarch64-linux | /gnu/store/7l33x1zjqn74m4f3dndcblbvnnqyyjr1-verilator-4.108.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes |