Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/sdw0f4bywrjd87j21069xxfq4xfh0zfd-verilator-4.108.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/k97j7b91wri29bd0l4kb32i07rax0k73-verilator-4.108.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/x58j5qknzjdqqlpp6g7yh5zsjhywd1fw-verilator-4.108.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/i6s6xh1aiqydxn9q6vkgh0hp7mn46sq9-verilator-4.108.drv | |
mips64el-linux | /gnu/store/1mcnas88p60zxzgbxpzbs3mr5183jc30-verilator-4.108.drv | ||
i686-linux | /gnu/store/m1dvx0as376kyg531f7qfkhsssaba05w-verilator-4.108.drv | ||
i586-gnu | /gnu/store/q609y0f209rlay1aq2z65sggv8k2f51l-verilator-4.108.drv | ||
armhf-linux | /gnu/store/nig7a2xbd9axcmw12yby1r5pdnz1v1qm-verilator-4.108.drv | ||
aarch64-linux | /gnu/store/zxm5r5q7fycch1j8rnfk1xws237whyjf-verilator-4.108.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes |