Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/84m312qiiwb2lscq36xzanifjkjlyxmb-verilator-4.110.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/agngqz4p5rs7fvaifawk7m9m7xawzpia-verilator-4.110.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/n67a815skw9xckga9q8nqkrz6yhf1lix-verilator-4.110.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/0814ifxq907c3mwpfkdd0jnbhnz2xzjv-verilator-4.110.drv | |
powerpc64le-linux | /gnu/store/4mxjnmf5503jgb4qkwixis3spf1ddkq6-verilator-4.110.drv | ||
mips64el-linux | /gnu/store/2a9vhpz1vwx0dkmj29maav7yr8m3mr9c-verilator-4.110.drv | ||
i686-linux | /gnu/store/v02h76yrrr8x49radladvnq5501py7hh-verilator-4.110.drv | ||
i586-gnu | /gnu/store/8ahhq5f3gal7h8jh9y2h8ysc4iwmahas-verilator-4.110.drv | ||
armhf-linux | /gnu/store/99kcqc3dm1kfax14aps8bif9dyb81r1l-verilator-4.110.drv | ||
aarch64-linux | /gnu/store/j487sjns83m1b80v8wqi4damh57zd0rq-verilator-4.110.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes |