Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/yi8kxnjqpw8qhc8ddgypg4krql234sjj-verilator-4.110.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/f0bcb004w76l28zyg730h95mpaj69vav-verilator-4.110.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/8r0fl6gh9yal6g9x0jjb60pcp6cnmfzb-verilator-4.110.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/n08qd2bhfm683kf6v9z023ny5qwck7mr-verilator-4.110.drv | |
mips64el-linux | /gnu/store/g43dpfa8c2qs1q9p9icgddyb3knjziar-verilator-4.110.drv | ||
i686-linux | /gnu/store/88nh08m1pmyx8zv5236xl6isyajxi5bw-verilator-4.110.drv | ||
i586-gnu | /gnu/store/lkx4l2l1bf5y324h431n7kbwnk7ysyqb-verilator-4.110.drv | ||
armhf-linux | /gnu/store/0dhhkmwh98ri76ycj127ilslfqahd9a3-verilator-4.110.drv | ||
aarch64-linux | /gnu/store/93s1yc1apv74b0xdm39zyn0zh3d3sx96-verilator-4.110.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes | |
description Validate package descriptions | use @code or similar ornament instead of quotes |