Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/00l6masi0vpv8lq43pgcgx5l4z8p8g8k-verilator-4.204.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/hjc2fky43jbkqf4q4pbxh7mnyy9n9bzn-verilator-4.204.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/s1g4nyqk7shlv3kr3qmwdilqgxhrw2vw-verilator-4.204.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/r4n6g9yawg0rhvjs7xdd5gygfs0pzhbm-verilator-4.204.drv | |
powerpc64le-linux | /gnu/store/qcry3vic2s59ah1rwc3570g93pb66s0l-verilator-4.204.drv | ||
mips64el-linux | /gnu/store/a3qh73k80mc6883lszlpadr02xwqxz9b-verilator-4.204.drv | ||
i686-linux | /gnu/store/z11hj00hahfhj8bhgnzjzk0fqp4lvr70-verilator-4.204.drv | ||
i586-gnu | /gnu/store/p5pn8r5fn402ym25pxr3744zgjsa5cr5-verilator-4.204.drv | ||
armhf-linux | /gnu/store/jjccqm8dchvi3k4xvv4zqxfrbymk403h-verilator-4.204.drv | ||
aarch64-linux | /gnu/store/larcx3k9v84xvm74h1s9hapg1i61mc2n-verilator-4.204.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes | |
description Validate package descriptions | use @code or similar ornament instead of quotes |