Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/9ynh0zwnl5j0ja6adwg8x6n54j2hjgz2-verilator-4.110.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/rzrlj9nc32awh2mgysmbvh79384acmn4-verilator-4.110.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/09sb1k5y3ahrxrq066zprgfpkv90dcpr-verilator-4.110.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/zhamaffdc630gaqasmidvnfv6qy1javs-verilator-4.110.drv | |
powerpc64le-linux | /gnu/store/k7qif0023jhxj4kcrpfi5k3p12c9g4gf-verilator-4.110.drv | ||
mips64el-linux | /gnu/store/hx0gzdz2g1alhsh4xnn7sz37dwciz39y-verilator-4.110.drv | ||
i686-linux | /gnu/store/q6vjbwfzqz2fxydc423gvvg9a6nd657x-verilator-4.110.drv | ||
i586-gnu | /gnu/store/phds3y9pv4jwf50hmzil6wbp7h9m6k2i-verilator-4.110.drv | ||
armhf-linux | /gnu/store/a5749c5gpg5yv9q7rmkyxgb7qqrzcqfs-verilator-4.110.drv | ||
aarch64-linux | /gnu/store/zrwyar10pbki93qrkcsn3mqjnb4gpsz2-verilator-4.110.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes |