Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/rl1y0190xrnb73cz499w9mwyq3prpcnf-verilator-4.204.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/zv544nh7783n6m1mba1dawbw64ybs7sl-verilator-4.204.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/fg60yd22z6vhs0akx06izjwldrkk0jpl-verilator-4.204.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/4j1g9wcsq6jwxl3hf9m0yjxs6zbv3257-verilator-4.204.drv | |
powerpc64le-linux | /gnu/store/afiy5xx3wa7118h0vnfhbbawnzaj972f-verilator-4.204.drv | ||
mips64el-linux | /gnu/store/2hvv3k8a808pnl83xj2d69s1ais40hp9-verilator-4.204.drv | ||
i686-linux | /gnu/store/4hm6hx2xpmn2c57iily1rg0ik161qinl-verilator-4.204.drv | ||
i586-gnu | /gnu/store/lwd8rg3llgx1j94mz6n0q7y22x4dh49b-verilator-4.204.drv | ||
armhf-linux | /gnu/store/y8ikxi6smgi83l1383gi8rbw5cjy5idd-verilator-4.204.drv | ||
aarch64-linux | /gnu/store/x69dzrbh5zy8lhsci7wwvz91sci07jsz-verilator-4.204.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes | |
description Validate package descriptions | use @code or similar ornament instead of quotes |