Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/cfpc1mxfrdvz9hw1dq6sdpnlalhsldv1-verilator-4.204.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/2brmmsln6ngxbbj6ncq6h6pazbv4svv9-verilator-4.204.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/mpgdq7hmjq9jhzmrjd4miblys46sm27g-verilator-4.204.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/lbxfy203i5h5bvkivbspa5dwyf5rbbyn-verilator-4.204.drv | |
powerpc64le-linux | /gnu/store/1a5zccjq4a9qj52hf26mgd5ykvr8s18a-verilator-4.204.drv | ||
mips64el-linux | /gnu/store/1vz0wrmqqvvyy08x7xr39rwgiyk1xcgm-verilator-4.204.drv | ||
i686-linux | /gnu/store/n9ipx4n11riggznflmq5d876hxhx0awd-verilator-4.204.drv | ||
i586-gnu | /gnu/store/p5k6c4q00jb881wfgq7w9qj7pn2ln9jh-verilator-4.204.drv | ||
armhf-linux | /gnu/store/ycy2ji4j4rgp98qw5znvcgcnjybcbbia-verilator-4.204.drv | ||
aarch64-linux | /gnu/store/gc1f4inyckkp4yk2vyq0vgzrn7g5cj8n-verilator-4.204.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes | |
description Validate package descriptions | use @code or similar ornament instead of quotes |