Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/v64vcqgz3qh8zwn8ki1a5qkm1mwgz2qx-verilator-4.110.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/70yxc8240pdzsnwgaj3kp02xskcv1a8h-verilator-4.110.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/gh9xpmqk9jwiy72sjlklbgifan1n9k3l-verilator-4.110.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/nakqil2qhbayw89pgq58j0x08gd3yhw3-verilator-4.110.drv | |
powerpc64le-linux | /gnu/store/m0bfhlwjnmhplihmh8ib47ga90i9camn-verilator-4.110.drv | ||
mips64el-linux | /gnu/store/hwd4irxj9axrvh3jiavcfya6pfzshqg8-verilator-4.110.drv | ||
i686-linux | /gnu/store/3qn9xzqvalvv3bianm9id9snm2f89nl8-verilator-4.110.drv | ||
i586-gnu | /gnu/store/d1jqjj3y558wk1y80rzh9hw326z68958-verilator-4.110.drv | ||
armhf-linux | /gnu/store/cjz4k7nmrkbbzp07cn3kplrbfkhm2vbq-verilator-4.110.drv | ||
aarch64-linux | /gnu/store/4d5z2pg77rk6yq8g9r6agvd28akarsln-verilator-4.110.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes | |
description Validate package descriptions | use @code or similar ornament instead of quotes |