Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/rdya5r601vcbcs4f6rn4qg2n3hslrh49-verilator-4.204.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/xxyfdzrqwd1lp92k0bqanikzk0bvpgdw-verilator-4.204.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/f9wr4zq0y0ggsmwbbyy127q2s626g58y-verilator-4.204.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/g0lqwapclwwms9m6w7h9ss8a2y3w7jyr-verilator-4.204.drv | |
powerpc-linux | /gnu/store/9ggq723fl97xrnks3j9xpg2mwykm3jfy-verilator-4.204.drv | ||
powerpc64le-linux | /gnu/store/d9hiskj7s7ycyl6674gzrsqq6axg800z-verilator-4.204.drv | ||
mips64el-linux | /gnu/store/55vw2ifycx4kgyg2x50p64nqi3y7gmi1-verilator-4.204.drv | ||
i686-linux | /gnu/store/qd965bkrqbkpa70lm8b4fb3b7mxr9wdj-verilator-4.204.drv | ||
i586-gnu | /gnu/store/sighdhayjzb7d6s8d5scipf0m43c4da5-verilator-4.204.drv | ||
armhf-linux | /gnu/store/aw0mlgprj4h5cgrnjf2qvka1kbpl6ann-verilator-4.204.drv | ||
aarch64-linux | /gnu/store/dxnmffpq5pns0sjk4dhzi9sd5a4scq73-verilator-4.204.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes | |
input-labels Identify input labels that do not match package names | label 'gettext' does not match package name 'gettext-minimal' |