Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/yigsq6kj3n0fyxvycg6k2fx02j5vmq9a-verilator-4.204.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/c22zb94r09wq7f1vvdglrfsjajyrdgkv-verilator-4.204.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/xh24cm1iqslcacr57f97ijrasf7byjn4-verilator-4.204.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/lhsj6i2n5rnh085vml28p0n7lfy6j8aa-verilator-4.204.drv | |
powerpc64le-linux | /gnu/store/52s2d0m68bp016g8dx72wl89255ab9if-verilator-4.204.drv | ||
mips64el-linux | /gnu/store/bf2ld8chx6dh7fpasaznwlqip1h4a41n-verilator-4.204.drv | ||
i686-linux | /gnu/store/319d1d6673s59z4jr9qsn0i9g3l9yki2-verilator-4.204.drv | ||
i586-gnu | /gnu/store/4mij6nr3crkl914zziasvgrfr2mlnli5-verilator-4.204.drv | ||
armhf-linux | /gnu/store/yqlqjgrbc1410z8wvrkxdjmyg9cvxzah-verilator-4.204.drv | ||
aarch64-linux | /gnu/store/hri0kqfk8b96n54wnzrf0lamx438z1rr-verilator-4.204.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes | |
description Validate package descriptions | use @code or similar ornament instead of quotes |