Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/ahk9l9v2h9f24hwghscn1zra0zq1ihnb-verilator-4.204.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/ziflm6sbab64qr08pv14kj4av6xfhwjc-verilator-4.204.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/d0334dkdslax7ij6s1ba183rq3zjya76-verilator-4.204.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/wz9n5wlx0f637vp6g5x28b2hkalkx0d0-verilator-4.204.drv | |
powerpc64le-linux | /gnu/store/xgjgp460rwfral9m8a7vj9s1yr00v2p4-verilator-4.204.drv | ||
mips64el-linux | /gnu/store/j9bcrh5cb8mdfa7wsgl8gysgs78js05p-verilator-4.204.drv | ||
i686-linux | /gnu/store/nv4v354656rbb6f2aqbnx01d0dx3fwib-verilator-4.204.drv | ||
i586-gnu | /gnu/store/5mkpldbldalxcwzswvlg8rf1wxm92ji7-verilator-4.204.drv | ||
armhf-linux | /gnu/store/q2y8zawgnl1i67p90d7s29hvhppw1j0c-verilator-4.204.drv | ||
aarch64-linux | /gnu/store/fw75x670czbsvlznxa5g65xz0flwp1gq-verilator-4.204.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes |