Fast Verilog/SystemVerilog simulator
Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp
and .h
files, the ``Verilated'' code.
The user writes a little C++/SystemC wrapper file, which instantiates the Verilated model of the user’s top level module. These C++/SystemC files are then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable performs the design simulation. Verilator also supports linking its generated libraries, optionally encrypted, into other simulators.
System | Target | Derivation | Build status |
---|---|---|---|
x86_64-linux | /gnu/store/gjbzbzdsv5g6wvqysqmzpf76xllx5xdm-verilator-4.204.drv | ||
x86_64-linux | i586-pc-gnu | /gnu/store/4d2rmx1ca3dxjm9mq4ai5b3qkwb2h905-verilator-4.204.drv | |
x86_64-linux | arm-linux-gnueabihf | /gnu/store/nbhcdp1i0is93rx7hn5cawp6ngd93ns8-verilator-4.204.drv | |
x86_64-linux | aarch64-linux-gnu | /gnu/store/b3cjc4nrgll2gpirji9g1l9pvklrackk-verilator-4.204.drv | |
powerpc64le-linux | /gnu/store/63ymaif4lvwg12sx3y3hr8vfaa49a06d-verilator-4.204.drv | ||
mips64el-linux | /gnu/store/lwvcd3324z53ai8j4b9g76g4wwj468qj-verilator-4.204.drv | ||
i686-linux | /gnu/store/r0sq1smvpaf1szjk4w3in9rv3hz33qc4-verilator-4.204.drv | ||
i586-gnu | /gnu/store/fiia4fpgq72fvfxkpyih1n2x3cn8r0zp-verilator-4.204.drv | ||
armhf-linux | /gnu/store/ia9ac2645ac7qn2qli5v1gh1g09p3sh8-verilator-4.204.drv | ||
aarch64-linux | /gnu/store/8ifspks5y0dhkvgknrf916km55q2q3p1-verilator-4.204.drv |
Linter | Message | Location |
---|---|---|
description Validate package descriptions | use @code or similar ornament instead of quotes |